rev. 2c august 31, 2004 www.fairchildsemi.com features 7.6mhz 5th order rgb/yuv/yc cv ?ters 50db stopband attenuation at 27mhz on all outputs better than 0.5db ?tness to 4.2mhz on all outputs no external frequency selection components or clocks ac coupled inputs and ac or dc coupled outputs supports both ntsc and pal luminance bandwidth continuous time low pass ?ters for video anti-aliasing or reconstruction applications <1% differential gain with 0.5?differential phase on all channels integrated dc restore circuitry with low tilt applications cable set top boxes satellite set top boxes terrestrial set top boxes dvd players personal video recorders (pvr) video on demand (vod) description the fms6408 provides three video signal paths including a two-input mux, a video ?ter and a 6db gain output driver. the ?ter bandwidth supports rgb and yuv signals in either ntsc or pal formats. the video ?ters approximate a 5th order butterworth low pass characteristic optimized for minimum overshoot and ?t group delay to provide excellent image quality. four different peaking options are available. the video ?ters can be bypassed if desired. in a typical application, the rgb or yuv dac outputs are ac coupled into the ?ters through the input mux. all channels have dc restore circuitry to clamp the dc input levels during video sync. the clamp pulse derived from the selected y input controls three independent feedback clamps. all outputs are capable of driving 2v pp , ac or dc coupled, into either a single (150 ? ) or dual (75 ? ) video load. the fms6408 clamp levels can be factory programmed for yuv /rgb (250mv for all channels), yc / ypbpr (250mv on channel 1 and 1.125v on channels 2 and 3) or yc cv (250mv on channels 1 and 3 and 1.125v on channel 2). fms6408 triple video filter driver for rgb and yuv signals functional block diagram 8mhz * sync processing 6d b gm 250mv y out y ina y inb 6d b gm u out u ina u inb 6d b gm 250mv or 1.125v * v out v ina v inb bypass (bypass/filter) in mux (a/b) * factory selected clamp and peaking levels 250mv or 1.125v * 8mhz * 8mhz *
2 rev. 2c august 31, 2004 data sheet fms6408 notes 1. 100% tested at 25?. 2. mode selection for yuv/rgb vs. pbpr/yc vs. yc cv operation based on factory programming 3. peaking options boost gain by 0db, 0.4db, 0.9db, or 1.3db from 4.2mhz to 5mhz based on factory programming electrical speci?ations (t c = 25?c, v i = 1v pp , v cc = 5.0v, all inputs ac coupled with 0.1 f, all outputs ac coupled with 220 f into 150 ? , referenced to 400khz, 0db peaking option; unless otherwise noted) ac electrical speci?ations (t c = 25?c, v i = 1v pp , v cc = 5.0v, all inputs ac coupled with 0.1 f, all outputs ac coupled with 220 f into 150 ? , referenced to 400khz, 0db peaking option; unless otherwise noted) symbol parameter conditions min typ max units i cc supply current 1 v cc no load 52 86 ma v i input voltage max 1.4 v pp v il digital input low 1 bypass, a_nb 0 0.8 v v ih digital input high 1 bypass, a_nb 2.0 v cc v v clamp clamp voltage 2 yuv/rgb/cv inputs 250 mv pbpr/c inputs 1.125 v psrr power supply rejection ratio dc -40 db symbol parameter conditions min typ max units a pb passband response 1 4.2mhz -0.5 0 db av lf low frequency gain (all channels) 1 at 400khz 5.6 5.9 6.2 db ? av hf delta high frequency at 5mhz (all channels) 3 0db peaking option 0.3 db 0.4db peaking option 0.7 db 0.9db peaking option 1.2 db 1.3db peaking option 1.6 db f c -3db bandwidth all channels 7.6 mhz f sbh stopband rejection (all channels) 1 at 27mhz 48 52 db dg differential gain all channels 0.2 % d differential phase all channels 0.5 thd total harmonic distortion at 3.58mhz 0.2 % snr snr all channels (ntc7 weighted) 4. 2mhz lowpass, 100khz highpass 75 db h dist line-time distortion 18 s, 100 ire bar tbd % v dist field-time distortion 130 lines, 18 s, 100 ire bar tbd % t pd propagation delay (all channels) 400khz 65 ns gd group delay (all channels) to 3.58mhz (ntsc) 14 ns t skew t pd skew between any 2 channels at 400khz 2ns a v(match) channel gain matching 1 400khz 0 5 % t clamp clamp response time (all channels) settled to 10mv, initial condition 0v 5 ms x talk crosstalk (channel-to-channel) at 1.0mhz -65 db in muxiso input mux isolation at 1.0mhz -85 db f 1dbwb bypass mode -1db bandwidth 1.4v pp output all channels 25 mhz
rev. 2c august 31, 2004 3 fms6408 data sheet absolute maximum ratings (beyond which the device may be damaged) note functional operation under any of these conditions is not implied. performance and reliability are guaranteed only if operatin g conditions are not exceeded. reliability information recommended operating conditions parameter min max units v cc -0.3 6 v analog and digital -0.3 v cc + 0.3 v output current any one channel (do not exceed) 50 ma input source resistance (r s )300 ? parameter min typ max units junction temperature +150 c storage temperature range -65 +150 ? lead temperature (soldering, 10s) +300 ? thermal resistance ( ja ), jedec standard multi-layer test boards, still air 90 ?/w parameter min typ max units temperature range 0 70 c v cc range +4.75 +5.0 +5.25 v factory programming options (see ordering information table on page 9 for current options) note these factory programming options allow a single die to be configured for multiple operating modes. part name part number clamping mode peaking mode (db) y out level (mv) u out level (v) v out level (v) fms6408-1 fms6408mtc141_nl ypbpr/yc 0 250 1.125 1.125 fms6408-2 FMS6408MTC142_nl ypbpr/yc 0.4 250 1.125 1.125 fms6408-3 fms6408mtc143_nl ypbpr/yc 0.9 250 1.125 1.125 fms6408-4 fms6408mtc144_nl ypbpr/yc 1.3 250 1.125 1.125 fms6408-5 fms6408mtc145_nl yuv/rgb 0 250 250 250 fms6408-6 fms6408mtc146_nl yuv/rgb 0.4 250 250 250 fms6408-7 fms6408mtc147_nl yuv/rgb 0.9 250 250 250 fms6408-8 fms6408mtc148_nl yuv/rgb 1.3 250 250 250 fms6408-9 fms6408mtc149_nl yc/cv 0 250 1.125 250 fms6408-10 fms6408mtc1410_nl yc/cv 0.4 250 1.125 250 fms6408-11 fms6408mtc1411_nl yc/cv 0.9 250 1.125 250 fms6408-12 fms6408mtc1412_nl yc/cv 1.3 250 1.125 250
4 rev. 2c august 31, 2004 data sheet fms6408 typical performance characteristics (t c = 25?c, v i = 1v pp , v cc = 5.0v, all inputs ac coupled with 0.1 f, all outputs ac coupled with 220 f into 150 ? , referenced to 400khz, 0db peaking option; unless otherwise noted) sd group delay vs. frequency -60 -40 -20 0 20 40 60 delay (ns) 400khz 5 10 15 25 20 30 frequency (mhz) 1 sd frequency response 2 -50 -40 -30 -20 10 gain (10db/div) 400khz 5 10 15 25 20 30 frequency (mhz) 0 -10 1 mkr freq. gain ref 400khz 6db 1 6.91mhz -1db bw 2 7.8mhz -3db bw 3 27mhz -43.24db f sbsd = gain (ref) ?gain (3) = 49.24db 3 differential gain (%) -0.8 0.2 0 -0.2 -0.4 -0.6 1st sd differential gain 2nd 3rd 4th 5th 6th ntsc min = -0.61 max = 0.00 ppmax = 0.61 sd noise vs. frequency -80 noise (db) -100 -120 -90 -70 0 1.0 2.0 3.0 4.0 5.0 6.0 frequency (mhz) -110 -60 -50 min = -0.13 max = 0.00 ppmax = 0.13 0.05 differential phase (deg) -0.20 0 1st sd differential phase 2nd 3rd 4th 5th 6th -0.05 -0.10 -0.15 bypass mode frequency response 2 0 1 2 3 4 5 6 7 gain (1db/div) 400khz 5 10 15 20 25 30 35 40 45 frequency (mhz) 1 mkr frequency gain ref 400khz 6db 1 28.75mhz -1db bw 2 36.94mhz -3db bw v o = 1.4 pp bypass mode group delay vs. freq. 0 14 16 delay (ns) 400khz5 1015202530354045 frequency (mhz) 1 = 25mhz (8.99ns) 1 = 7.6mhz (31.88ns) 12 10 8 6 4 2 1
rev. 2c august 31, 2004 5 fms6408 data sheet pin con?uration pin# pin type description 1y ina input y (luminance) or green input a, must be connected to a signal which includes sync 2u ina input u or blue input a 3v ina input v or red input a 4 gnd input must be tied to ground, do not float 5y inb input y (luminance) or green input b, must be connected to a signal which includes sync 6u inb input u or blue input b 7v inb input v or red input b 8in mux (a/b ) input mux select, a = ?? b = ?? must be externally tied high or low 9v out output v or red output 10 gnd input must to be tied to ground, do not float 11 u out output u or blue output 12 bypass (bypass/filter ) input filter bypass, bypass = ?? filter = ?? must be externally tied high or low 13 y out output y or green output 14 v cc input +5v supply functional description introduction this product is a three channel monolithic continuous time video ?ter designed for reconstructing yuv, yc cv or rgb signals from a video d/a source. inputs should be ac coupled while outputs can be either ac or dc coupled. the reconstruction ?ters approximate a 5th order butter- worth response optimized for minimum overshoot and ?t group delay. this provides a maximally ?t response in terms of delay and amplitude. each of the three outputs is capable of driving 2v pp into 75 ? loads. all channels are clamped during the sync interval to set the appropriate dc output level. sync tip clamping greatly reduces the effective input time constant allowing the use of small low cost input coupling capacitors. the input will settle to 10mv in 2ms for typical dc shifts present in the video signal. in most applications the input coupling capacitors are 0.1 f. the inputs typically sink 1ua of current during active video. for yuv signals, this translates into a 2mv tilt in a horizon- tal line at the y output. during sync, the clamp restores this leakage current by sourcing an average of 20 a over the clamp interval. any change in the coupling capacitor values will affect the amount of tilt per line. any reduction in tilt will come with an increase in settling time. sync processing is based on the y/g input channel in all operating modes. inputs the inputs will typically be driven by either a low impedance source of 1v pp or the output of a 75 ? terminated line driven by the output of a current dac. in either case, the inputs must be capacitively coupled to allow the sync-detect and dc restore circuitry to operate properly. outputs the outputs are low impedance voltage drivers which can handle either a single or dual load. a single load consists of a 75 ? series termination resistor feeding a 75 ? terminated line for a total load at the part of 150 ? . even when two loads are present (75 ? ) the driver will produce a full 2v pp signal at its output pin. the driver can also be used to drive an ac coupled single or dual load. when driving a dual load either output will still function if the other output connection is inadvertently shorted providing these loads are ac coupled. fms6408 14-pin tssop y ina v cc u ina v ina bypass gnd y inb gnd in mux (a/b) u inb v inb y out u out v out 1 2 3 4 5 6 7 14 13 12 11 10 9 8
6 rev. 2c august 31, 2004 data sheet fms6408 0.1uf y ina y inb u ina u inb v ina v inb 220uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 220uf 220uf fms6408 14l tssop y ina v cc u ina v ina bypass gnd y inb gnd in mux (a/b) 14 13 12 11 10 9 8 1 2 3 4 5 6 7 u inb v inb y out u out v out 0.1 uf 1.0 uf +5v 300k 10k typical application diagrams figure 1. ac-coupled yuv line driver with single video loads figure 2. dc-coupled yuv line driver with dual video loads 75 0.1uf y ina y inb u ina u inb v ina v inb 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf +5v 75 video cables 75 fms6408 14l tssop y ina u ina v ina bypass gnd y inb gnd 14 13 12 11 10 9 8 1 2 3 4 5 6 7 u inb v inb y out u out v out 0.1 uf 1.0 uf 75 75 75 75 75 75 75 75 75 75 v cc in mux (a/b) 300k ? 10k ?
rev. 2c august 31, 2004 7 fms6408 data sheet +5v v cc y out u out v out 75 ? 75 ? video cables 75 ? 75 ? 75 ? 75 ? 75 ? 75 ? 75 ? 75 ? 75 ? 75 ? 75 ? driver driver driver i y i u i v + vi y - + vi u - + vi v - 0.25v 0.85v 1.55v 2.25v 0.425v 1.125v 1.825v 0.425v 1.125v 1.825v application notes output drive capability the fms6408 can drive dual 75 ? loads where each load consists of a 75 ? resistor in series with a 75 ? termination resistor in the driven device. this presents a 150 ? load to the output so two similar loads in parallel look like 75 ? from the output to ground. in some cases it may be desirable to drive a single load on one or more outputs with a dual load on the remaining outputs. this is an acceptable loading con- dition but might cause a slight degradation in gain matching. device power dissipation the fms6408 speci?ations provide a quiescent no-load supply current of 52ma (typical). with a nominal 5v supply, this results in a power dissipation of 260mw. the overall power dissipation can be signi?antly affected by the applied load, particularly in dc-coupled applications. in order to calculate the total power dissipation the typical output voltages and the loading must be known. the highest power dissipation will occur for yuv video sig- nals that are dc-coupled into dual video loads. refer to the the diagram in figure 3 below. assume a video signal on the y channel that averages 50% luminance with an output voltage of 1.55v then calculate the load current: i load (y) = 1.55v/75 ? = 20.6ma the device dissipation due to this load will be the internal voltage drop multiplied by the load current: p diss (y) = (5v - 1.55v) * 20.6ma = 71mw the average dc level for the u and v channels is set by the clamp circuit to 1.125v. the signal will be symmetrical about this voltage so: i load (u) = 1.125v/75 ? = 15ma the device dissipation due to this load will be the internal voltage drop multiplied by the load current: p diss (u) = (5v - 1.125v) * 15ma = 58.125mw since the u and v power dissipation are approximately the same, the total dissipation due to the load can be estimated by: p diss (load) = p (y) + 2 * p (u) = 71mw + (2 * 58.125mw) = 187.55mw this will bring the typical total device power dissipation to 260mw (quiescent power) + 187.55mw (load power) or 447.55mw. it is advisable to calculate the highest possible power dissipation using worst-case quiescent supply current and the maximum allowable power supply voltage. this result should be used when calculating the die temperature rise with the supplied ja , thermal resistance value. field time distortion in applications with ac-coupled outputs, the ac-coupling capacitors will dominate the ?ld time distortion. perfor- mance is speci?d with 220 f coupling capacitors; if better performance is desired, the capacitors may be increased or the outputs may be dc-coupled. figure 3. yuv video signals that are dc-coupled into dual video loads
8 rev. 2c august 31, 2004 data sheet fms6408 e/2 2x ddd c b a 6 6 1.0 1.0 123 9 e /2 e1 e e n 8 ?b 7 2x n/2 tips 1.0 dia ?a 7 ?c aaa c ccc 83 d cb a bbb m b nx a1 a2 a c1 c (b) b1 5 section aa 10 a a ?h gage plane 0.25 (0.20) (02) r1 r 01 (l1) l (03) notes: 1 all dimensions are in millimeters (angle in degrees). 2 dimensioning and tolerancing per asme y14.5?994. 3 dimensions "d" does not include mold flash, protusions or gate burrs. mold flash protusions or gate burrs shall not exceed 0. 15 per side . 4 dimension "e1" does not include interlead flash or protusion. interlead flash or protusion shall not exceed 0.25 per side. 5 dimension "b" does not include dambar protusion. allowable dambar protusion shall be 0.08mm total in excess of the "b" dimens ion at maximum material condition. dambar connot be located on the lower radius of the foot. minimum space between protusion and adjacent lead is 0.07mm for 0.5mm pitch packages. 6 terminal numbers are shown for reference only. 7 datums ?a ? and ?b ? to be determined at datum plane ?h ?. 8 dimensions "d" and "e1" to be determined at datum plane ?h ?. 9 this dimensions applies only to variations with an even number of leads per side. for variation with an odd number of leads p er side, the "center" lead must be coincident with the package centerline, datum a. 10 cross sections a ?a to be determined at 0.10 to 0.25mm from the leadtip. symbol min nom max a ? ? 1.10 a1 0.05 ? 0.15 a2 0.85 0.90 0.95 l 0.50 0.60 0.75 r 0.09 ? r1 0.09 ? b 0.19 ? 0.30 b1 0.19 0.22 0.25 c 0.09 ? 0.20 c1 0.09 ? 0.16 01 0 8 l1 1.0 ref aaa 0.10 bbb 0.10 ccc 0.05 ddd 0.20 e 0.65 bsc 02 12 ref 03 12 ref mtc-14 d 4.90 5.00 5.10 e1 4.30 4.40 4.50 e 6.4 bsc e 0.65 bsc n 14 package dimensions mtc-14
www.fairchildsemi.com ?2004 fairchild semiconductor corporation fms6408 data sheet disclaimer fairchild semiconductor reserves the right to make changes without further notices to any products herein to improve reliabilit y, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described h erein; neither does it convey any license under its patent rights, nor the rights of others. life support policy fairchild? products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: ordering information temperature range for all parts: 0? to +70?. contact fairchild for ordering information regarding other clamping and peaking options. refer to the factory programming opti ons table on page 3 for a detailed description of available options. model part number lead free mode output peaking package container pack qty fms6408 fms6408mtc141_nl yuv/rgb 0db tssop-14 tube 94 fms6408 fms6408mtc141x_nl yuv/rgb 0db tssop-14 tape and reel 2500 fms6408 fms6408mtc143_nl yuv/rgb 0.9db tssop-14 tube 94 fms6408 fms6408mtc143x_nl yuv/rgb 0.9db tssop-14 tape and reel 2500 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to per form when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a signi?ant injury of the user. 2. a critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
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